1. Field of the Invention
The invention relates to an electrically rewritable non-volatile semiconductor memory device (EEPROM), such as a flash memory, etc, and a write-in method thereof.
2. Description of the Related Art
A highly integrated NAND-type non-volatile semiconductor memory device (refer to Patent Documents 1-4) which connects a plurality of memory cell transistors (hereinafter referred to as memory cells) to and between bit lines and source lines in series to form a NAND string is well known in the art.
In a common NAND-type non-volatile semiconductor memory device, when erasing, a high voltage, such as 20V, is applied to a semiconductor substrate and 0V is applied to a word line. As such, electrons are pulled out from a floating gate, i.e., a charge accumulation layer formed by poly-silicon material etc., and a threshold voltage is lower than an erasing threshold voltage (for example, −3V). In addition, in writing-in (programming), 0V is applied to the semiconductor substrate, and a high voltage, such as 20V, is applied to a control gate. As a result, electrons are injected from the semiconductor substrate into the floating gate, thereby making a threshold voltage higher than a write-in threshold voltage (for example, 1V). States of a memory cell which utilizes the threshold voltages may be determined by applying a readout voltage (for example, 0V) between the write-in threshold voltage and a readout threshold voltage to the control gate to determine whether a current is flowing through the memory cell.
For the described non-volatile semiconductor memory device, when writing-in to the memory cell, which is a write-in target, is performed through a programming operation, electrical charges are injected into the floating gate of the memory cell transistor and the threshold voltage increases. As a result, though a voltage which is lower than the threshold voltage is applied to the gate, there is no current flowing through the memory cell transistor, and a state where data ‘0’ is written is achieved. In general, the threshold voltage of the memory cell in an erasing state has variations, and a write-in speed also has variations according to process variations. Therefore, when the programming operation is performed by applying a predetermined write-in voltage and the threshold voltage is verified to be higher than a verify-level, the threshold voltage of the memory cell after write-in has a distribution above the verify-level.
Meanwhile, because of process variations, for a memory having a write-in speed with large variations, a more efficient write-in method, ISPP (Increment Step Pulse Program) method, is used. In other words, if processing variations regarding to manufacturing process is large, a threshold voltage distribution after the writing-in to the memory cell is increased by 1 pulse. Simply, though verify technology is used for every bit, when trying to control the threshold voltage to be narrow, it still has to repeat write-in/verify smoothly, and as a result, it is necessary to perform long-running writing-in. Therefore, as shown in FIG. 4, a method where voltages of programming pulses PP begin from a programming start voltage Vstart and are increased by a predetermined step voltage Vstep as verifying is performed for every bit is provided.